FIG. 1 is a demonstrative illustration of a top view of a known semiconductor device 1 including a CMOSFET 6 within a silicon substrate 2. CMOSFET 6 comprises a gate 5 between a first-heavily doped region 3, acting as a source, and a second heavily-doped region 3′, acting as a drain. Heavily-doped regions 3 and 3′ may include, for example, phosphorous-doped silicon carbide (SiC:P) in the case that CMOSFET 6 is n-type FET or SiGe:B in the case that CMOSFET 6 is a p-type FET.
Source 3 and drain 3′ each include a contact, 4 and 4′, respectively, and are connected to a common body 7. Common body 7 also includes a contact, 4″.
FIGS. 2 and 3 are demonstrative illustrations of cross-sectional views of semiconductor device 1 taken through axes A-A and B-B, respectively, of FIG. 1. One deficiency of the illustrated known device 1 is that the discharge path 8 (FIG. 3) of CMOSFET 6 is parallel to a width WG of gate 5. As a consequence, the resistance of discharge path 8 of CMOSFET 6 increases with increasing gate width.